In image data processing, pattern matching is often performed at various levels of processes. For example, when the RGB image data is converted into the YMCK recording image data and the YMCK image data is outputted to a printer for printing on a piece of paper, it is desirable to binarize the binary image such as characters and lines for clear image formation. On the other hand, for middle-level gradation images such as photographic images, dot presence or dot gradation is defined based upon binarization or a small number of gradations. It is desirable to express the smooth intensity change by a gradation process. A typical gradation process includes dithering, and the gradation process expresses area gradation by distributing and arranging a certain number of dots in a unit area. Of course, binary images such as characters and lines and bit-map images or middle-level gradation images such as photographs and pictures exist in the same original image. For this reason, based upon the RGB image data, an area separation unit automatically determines the binary image areas herein after referred to as character areas and middle-level gradation areas herein after referred to as picture areas. In the gradation process, the image data is automatically processed using a character area process or a picture area process based upon the above determination results.
In a pattern matching using conventional hardware, since the pixels to be matched are concurrently obtained and compared, a work memory area is necessary for the image data. In general, since images are raster scanned in an image device such as a copier and an input image data is based upon a raster unit, a work memory area is a line buffer. For example, for a 3×3 pixel matrix pattern matching, three lines of work memory are necessary. A determination window is generated for the matrix size, and the matching takes place on the window basis. Conceptually, from the three-line buffer memory, each pixel from a middle line is sequentially made as a current pixel. A 3×3 pixel matrix is defined with the current pixel that is located at the center of the matrix. For each pixel matrix, the contained image data for each pixel is compared to that of the reference patter to determine a match.
The above pattern comparison matching method generally includes two categories of approach. One category is that the circuits are arranged in parallel in order to generate the comparison results at a high speed. The other category is that a single circuit is repeatedly used in order to avoid a large circuit size. These two approaches have some setbacks. In the first approach, although the determination results are obtained at a high speed, it requires a number of circuits that corresponds to a number of pattern matching. As the number of matching patterns increases, the circuit becomes larger and complex. On the other hand, in the second approach, the processing speed is generally longer at the cost of a small size of the circuit. Even in the first approach, the comparison is sequential between the pixel matrix and the reference pattern, the processing time is still long for one of the image data. For this reason, it remains desirable to shorten the comparison process time.
Japanese Patent Publication 200-175043 discloses that each row of the image data in the M×N pixel matrix is latched in N units of row registers 113. By using a multiplexer 114, all of the latch outputs (M×N) from the N row registers 113 are arranged in a single row, and a determination unit 115 processes the single row of the reference data for a bit-to-bit comparison to obtain the match determination result. Furthermore, by latching two 5×5 pixel matrixes of image data that are odd-numbered and even-numbered pixels of the matrix register 713, the image data storage duplication is avoided. FIG. 7 of Japanese Patent Publication 200-175043 discloses that two determination units determine the pattern matching in parallel. Although the above method gains a high speed pattern matching, more hardware such as latch for matrix image data becomes necessary. As the pattern matching size increases, since the circuit size increases and the timing control becomes complex, the device becomes expensive. In addition, since the matching pattern size is fixed, the process is limited.
Japanese Patent Publications Hei 9-114967 and Hei 9-231356 disclose an image process method of distributed calculation for determining whether each row of the two-dimensional image data matches each row of the two-dimensional reference data using a parallel process DSP having a plurality of calculation units. By the above method, the circuit size is relative small, and it is flexible enough to deal with various sizes of pattern matching. However, in order to process the two-dimensional matrix data arrangement by the calculation unit of the processor, since it is necessary for the processor to rearrange the data, the pattern matching process takes an undesirable amount of time. One unit of the calculation unit processes only one bit of the binary data. For multi-bit multi-value image data in a photocopier, it is necessary to use a corresponding number of calculation units, and the processor control becomes complex. As a result, an undesirable long processing period of time is experienced. Furthermore, the multi-gradation image data to be processed by the image process potentially includes various gradation levels such as 64-gradataion, 128-gradation and 256-gradation. A processor that processes only 1-bit binarized data leaves the remaining gradations in the above multi-value data. It is difficult to flexibly perform the image data pattern matching of various gradations by changing a binarization threshold value.
To avoid the change in the range of the image separation signal, when the image area determination is corrected or smoothed for stably continuous results, in order to refer the image area determination of the preceding current pixel to that of the proceeding current pixel, an image process processor holds the image area determination result of the preceding current pixel. The result is combined with the image data of the current matrix, and the combined determination result is given to a look up table (LUT). The determination result data is read from the LUT. This slows down the image process speed of the image process processor. It is desirable to avoid the image process slow down.
In addition, the image data is read by a CCD and is converted to digital data by an A/D converter. The converted digital data is corrected for shading, and the shading correction data is determined in the following manner. One line of data is scanned by a scanner from a standard white board. A minimal value and a maximal value of the scanned image data are detected. Furthermore, a line of data is scanned without light, and a minimal value and a maximal value of the scanned image data are detected. A correction coefficient for each pixel on one line is determined based upon the scanned one-line standard white data and the above determined maximal and minimal values. The correction coefficient corrects the distortion in the scanning direction. The correction coefficient is stored in the shading correction memory and is read to apply to scanned image data. The determination of the above minimal and maximal values slows down the image process processor in handling the CCD scanned image data. The detection of the minimal and maximal values in an entire line or portions of the line of the image data is necessary for image processes other than the above shading correction coefficient. Obviously, it is desirable to avoid the image processor slow down in the determination of the minimal and maximal values.
One object of the current invention is to provide a small number of circuits for flexibly performing a pattern match on image data in various two-dimensional matrix formats at a high speed. Another object of the current invention is to provide a high-speed image area separation and to promote the stability in the image area determination.